diff options
| author | Kangheui Won <khwon@chromium.org> | 2021-05-14 15:17:50 +1000 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-07 05:16:20 +0000 |
| commit | 260f0f93efa809d6aab5220253ca74410d0027c2 (patch) | |
| tree | c04d7b31c9d2de76effb87066c17c41077197fed /src/soc/amd | |
| parent | 32f43e0e134eded6221dd59400b2a01860c72f76 (diff) | |
cezanne/psp_verstage: add reset/timer svc
The new cezanne PSP release added support for these svcs. So add those
functionality back to cezanne psp_verstage.
BUG=b:187906425
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/cezanne/psp_verstage/chipset.c | 16 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/psp_verstage/svc.c | 21 | ||||
| -rw-r--r-- | src/soc/amd/common/psp_verstage/Makefile.inc | 4 |
3 files changed, 20 insertions, 21 deletions
diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index c0593bf05a..7ad21490f8 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -8,8 +8,6 @@ #include <bl_uapp/bl_syscall_public.h> #include <console/console.h> #include <psp_verstage.h> -#include <reset.h> -#include <timer.h> uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) { @@ -35,17 +33,3 @@ uint32_t svc_write_postcode(uint32_t postcode) { return 0; } - -static uint64_t tmp_timer_value = 0; -void timer_monotonic_get(struct mono_time *mt) -{ - mt->microseconds = tmp_timer_value / 1000; - tmp_timer_value++; -} - -void do_board_reset(void) -{ - printk(BIOS_ERR, "Reset not implemented yet.\n"); - while (1) - ; -} diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index 70cb36983c..bd4bec5798 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -35,9 +35,8 @@ uint32_t svc_get_boot_mode(uint32_t *boot_mode) void svc_delay_in_usec(uint32_t delay) { - uint32_t i; - for (i = 0; i < delay * 1000; i++) - asm volatile ("nop"); + uint32_t unused = 0; + SVC_CALL1(SVC_DELAY_IN_MICRO_SECONDS, delay, unused); } uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info) @@ -97,3 +96,19 @@ uint32_t svc_save_uapp_data(void *address, uint32_t size) SVC_CALL2(SVC_COPY_DATA_FROM_UAPP, (uint32_t)address, size, retval); return retval; } + +uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value) +{ + unsigned int retval = 0; + assert(type < PSP_TIMER_TYPE_MAX); + SVC_CALL2(SVC_READ_TIMER_VAL, type, counter_value, retval); + return retval; +} + +uint32_t svc_reset_system(enum reset_type reset_type) +{ + unsigned int retval = 0; + assert(reset_type < RESET_TYPE_MAX); + SVC_CALL1(SVC_RESET_SYSTEM, reset_type, retval); + return retval; +} diff --git a/src/soc/amd/common/psp_verstage/Makefile.inc b/src/soc/amd/common/psp_verstage/Makefile.inc index 7272de4b69..678bc45f0f 100644 --- a/src/soc/amd/common/psp_verstage/Makefile.inc +++ b/src/soc/amd/common/psp_verstage/Makefile.inc @@ -14,10 +14,10 @@ verstage-y += post.c verstage-y += printk.c verstage-y += psp_verstage.c verstage-y += psp.c -ifneq ($(CONFIG_SOC_AMD_CEZANNE),y) -# cezanne PSP does not support these functions yet (b/187906425) verstage-y += reset.c verstage-y += timer.c +ifneq ($(CONFIG_SOC_AMD_CEZANNE),y) +# cezanne PSP does not support these functions yet (b/187906425) verstage-y += vboot_crypto.c endif |