diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-05-21 16:31:52 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-05-25 15:20:27 +0000 |
| commit | 0318dc169ec256108dcffd273efc5b83b3a54a58 (patch) | |
| tree | 1f3b6ee5f26da3f3ef3b5a57f2d1037ab20f0e67 /src/soc/amd | |
| parent | 0d93ca48c070847f156720a9cb15f9d5429615f4 (diff) | |
soc/amd/common/block/espi: Increase ESPI_CH_READY_TIMEOUT_US to 10ms
The ChromeEC might take longer than 1ms for the peripheral channel to be
enabled. The PLTRST# interrupt handler takes about ~539us.
This doesn't account for the time it takes for the interrupt handler
to be scheduled. Increasing the timeout to 10ms gives ample time.
BUG=b:188188172, b:188935533
TEST=Boot guybrush and no longer see channel enable errors
Suggested-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib6db577bf06175ceb17b446af706ad8c9f891481
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54788
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/lpc/espi_util.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 9bad4c2152..0ea014fee2 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -371,7 +371,7 @@ enum espi_cmd_type { #define ESPI_RXVW_POLARITY 0xac #define ESPI_CMD_TIMEOUT_US 100 -#define ESPI_CH_READY_TIMEOUT_US 1000 +#define ESPI_CH_READY_TIMEOUT_US 10000 union espi_txhdr0 { uint32_t val; |