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| author | Jamie Ryu <jamie.m.ryu@intel.com> | 2020-06-24 14:45:13 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-30 05:59:45 +0000 |
| commit | f8668e98902d0ac6589ca9652206468ab370e2f2 (patch) | |
| tree | d79ccba12bed7394784bd2ba1ce4c81086f4731f /src/soc/amd/stoneyridge | |
| parent | 3d6066eaccb641e001ab28a4b46d8f7f0e827f89 (diff) | |
soc/intel/tigerlake: Add CpuReplacementCheck to chip options
Add CpuReplacementCheck to chip options to control UPD FSPM
SkipCpuReplacementCheck from devicetree.
This UPD allows platforms with soldered down SoC to skip CPU
replacement check to avoid a forced MRC traning.
TEST=boot and verified with volteer
Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42788
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
0 files changed, 0 insertions, 0 deletions