soc/amd/*/uart: commonize UART code and MMIO device driver

Now that the SoC-specific UART controller data and the common code part
are cleanly separated, move the code to the common AMD UART support
block folder. The code is identical to the UART code in Cezanne,
Mendocino, Morgana and Picasso while Stoneyridge doesn't use the parts
related to the MMIO device driver.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9429dac44bc02147a839db89d06e8eded7f1af2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>

1 files changed, 1 insertions, 24 deletions

diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c
index 837a1bff7e..86e2626a50 100644
--- a/src/soc/amd/stoneyridge/uart.c
+++ b/src/soc/amd/stoneyridge/uart.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <amdblocks/aoac.h>
 #include <amdblocks/gpio.h>
 #include <amdblocks/uart.h>
 #include <soc/aoac_defs.h>
@@ -19,30 +18,8 @@ static const struct soc_uart_ctrlr_info uart_info[] = {
 		} },
 };
 
-static const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs)
+const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs)
 {
 	*num_ctrlrs = ARRAY_SIZE(uart_info);
 	return uart_info;
 }
-
-uintptr_t get_uart_base(unsigned int idx)
-{
-	size_t num_ctrlrs;
-	const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs);
-
-	if (idx >= num_ctrlrs)
-		return 0;
-
-	return ctrlr[idx].base;
-}
-
-void set_uart_config(unsigned int idx)
-{
-	size_t num_ctrlrs;
-	const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs);
-
-	if (idx >= num_ctrlrs)
-		return;
-
-	gpio_configure_pads(ctrlr[idx].mux, 2);
-}