soc/amd: Define post codes

For the most part, this doesn't change any post codes, simply making the
existing post-codes into macros.

picasso/romstage.c did get a couple of post codes removed to match the
other files.

The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global
at some point, while the POST_AGESA and POST_PSP codes would stay AMD
specific.

Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

3 files changed, 16 insertions, 13 deletions

diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c
index 0a67d9b24c..f5451f8590 100644
--- a/src/soc/amd/stoneyridge/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock.c
@@ -13,6 +13,7 @@
 #include <amdblocks/amd_pci_mmconf.h>
 #include <amdblocks/biosram.h>
 #include <amdblocks/iomap.h>
+#include <amdblocks/post_codes.h>
 #include <soc/pci_devs.h>
 #include <soc/cpu.h>
 #include <soc/southbridge.h>
@@ -77,7 +78,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 void bootblock_soc_early_init(void)
 {
 	bootblock_fch_early_init();
-	post_code(0x90);
+	post_code(POST_BOOTBLOCK_SOC_EARLY_INIT);
 }
 
 void bootblock_soc_init(void)
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index 1633ecddae..0a530fcc5a 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -15,6 +15,7 @@
 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/agesawrapper_call.h>
 #include <amdblocks/i2c.h>
+#include <amdblocks/post_codes.h>
 
 #include "chip.h"
 
@@ -115,15 +116,15 @@ struct chip_operations soc_amd_stoneyridge_ops = {
 static void earliest_ramstage(void *unused)
 {
 	if (!acpi_is_wakeup_s3()) {
-		post_code(0x46);
+		post_code(POST_PSP_LOAD_SMU);
 		if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
 			psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");
 
-		post_code(0x47);
+		post_code(POST_AGESA_AMDINITENV);
 		do_agesawrapper(AMD_INIT_ENV, "amdinitenv");
 	} else {
 		/* Complete the initial system restoration */
-		post_code(0x46);
+		post_code(POST_AGESA_AMDS3LATERESTORE);
 		do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore");
 	}
 }
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 54fc51ee99..efa256fb14 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -5,6 +5,7 @@
 #include <amdblocks/agesawrapper_call.h>
 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/biosram.h>
+#include <amdblocks/post_codes.h>
 #include <amdblocks/psp.h>
 #include <arch/romstage.h>
 #include <cbmem.h>
@@ -35,10 +36,10 @@ void __weak mainboard_romstage_entry(void)
 
 static void agesa_call(void)
 {
-	post_code(0x37);
+	post_code(POST_AGESA_AMDINITRESET);
 	do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
 
-	post_code(0x38);
+	post_code(POST_AGESA_AMDINITEARLY);
 	/* APs will not exit amdinitearly */
 	do_agesawrapper(AMD_INIT_EARLY, "amdinitearly");
 }
@@ -66,10 +67,10 @@ void __noreturn romstage_main(void)
 	bsp_agesa_call();
 
 	if (!s3_resume) {
-		post_code(0x40);
+		post_code(POST_AGESA_AMDINITPOST);
 		do_agesawrapper(AMD_INIT_POST, "amdinitpost");
 
-		post_code(0x41);
+		post_code(POST_AGESA_AMDINITPOST_DONE);
 		/*
 		 * TODO: This is a hack to work around current AGESA behavior.
 		 *       AGESA needs to change to reflect that coreboot owns
@@ -99,16 +100,16 @@ void __noreturn romstage_main(void)
 		wrmsr(SYSCFG_MSR, sys_cfg);
 	} else {
 		printk(BIOS_INFO, "S3 detected\n");
-		post_code(0x60);
+		post_code(POST_AGESA_AMDINITRESUME);
 		do_agesawrapper(AMD_INIT_RESUME, "amdinitresume");
 
-		post_code(0x61);
+		post_code(POST_AGESA_AMDINITRESUME_DONE);
 	}
 
-	post_code(0x42);
+	post_code(POST_PSP_NOTIFY_DRAM);
 	psp_notify_dram();
 
-	post_code(0x43);
+	post_code(POST_PSP_NOTIFY_DRAM_DONE);
 	if (cbmem_recovery(s3_resume))
 		printk(BIOS_CRIT, "Failed to recover cbmem\n");
 	if (romstage_handoff_init(s3_resume))
@@ -117,7 +118,7 @@ void __noreturn romstage_main(void)
 	if (CONFIG(SMM_TSEG))
 		smm_list_regions();
 
-	post_code(0x44);
+	post_code(POST_ROMSTAGE_RUN_POSTCAR);
 	prepare_and_run_postcar();
 }