diff options
| author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:53:22 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:07:08 +0000 |
| commit | 26f97f9532933da3c1d72a7918c8a24457bbc1c0 (patch) | |
| tree | 8c25279e58ef541fae197ec193f5642a9b21b2d4 /src/soc/amd/stoneyridge | |
| parent | 50863daef8ed75c0cb3dfd375e7622c898de5821 (diff) | |
src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 8 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 78ce889e5d..f7ea782da9 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -56,7 +56,7 @@ Name(CRES, ResourceTemplate() { * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 82c54371c5..b870baeb88 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -46,7 +46,7 @@ struct soc_amd_stoneyridge_config { * If sb_reset_i2c_peripherals() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. * For example, should we need I2C0 and I2C3 have their peripheral - * devices reseted by toggling SCL, use: + * devices reset by toggling SCL, use: * * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index d80aeb2a09..d5231ad5d5 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -400,19 +400,19 @@ void domain_read_resources(struct device *dev) reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); /* - * 0x100000 (1MiB) -> low top useable RAM + * 0x100000 (1MiB) -> low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ ram_resource(dev, idx++, (1 * MiB) / KiB, (mem_useable - (1 * MiB)) / KiB); - /* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */ + /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ reserved_ram_resource(dev, idx++, mem_useable / KiB, (tom.lo - mem_useable) / KiB); /* If there is memory above 4GiB */ if (high_tom.hi) { - /* 4GiB -> high top useable */ + /* 4GiB -> high top usable */ if (uma_base >= (4ull * GiB)) high_mem_useable = uma_base; else @@ -422,7 +422,7 @@ void domain_read_resources(struct device *dev) ram_resource(dev, idx++, (4ull * GiB) / KiB, ((high_mem_useable - (4ull * GiB)) / KiB)); - /* High top useable RAM -> high top RAM */ + /* High top usable RAM -> high top RAM */ if (uma_base >= (4ull * GiB)) { reserved_ram_resource(dev, idx++, uma_base / KiB, uma_size / KiB); |