soc/amd: move smi_util to common block

The functionality in smi_util applies for all 3 AMD SoCs in tree. This
patch additionally drops the HAVE_SMI_HANDLER guards in the common
block's Makefile.inc, since all 3 SoCs unconditionally select
HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any
functionality that is only present when that option is selected.

Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

3 files changed, 1 insertions, 130 deletions

diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index f24d202359..d672726e8c 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_CAR
 	select SOC_AMD_COMMON_BLOCK_S3
 	select SOC_AMD_COMMON_BLOCK_SMBUS
+	select SOC_AMD_COMMON_BLOCK_SMI
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 8cdf6ccdbe..969f5129eb 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -19,7 +19,6 @@ bootblock-y += enable_usbdebug.c
 bootblock-y += monotonic_timer.c
 bootblock-y += tsc_freq.c
 bootblock-y += southbridge.c
-bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 
 romstage-y += BiosCallOuts.c
 romstage-y += i2c.c
@@ -32,7 +31,6 @@ romstage-y += memmap.c
 romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 romstage-y += tsc_freq.c
 romstage-y += southbridge.c
-romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 romstage-y += psp.c
 
 verstage-y += gpio.c
@@ -61,7 +59,6 @@ ramstage-y += northbridge.c
 ramstage-y += sata.c
 ramstage-y += memmap.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 ramstage-y += usb.c
 ramstage-y += tsc_freq.c
@@ -72,7 +69,6 @@ all-y += reset.c
 
 smm-y += monotonic_timer.c
 smm-y += smihandler.c
-smm-y += smi_util.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_DEBUG_SMI) += uart.c
 smm-y += gpio.c
diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c
deleted file mode 100644
index 39b2b95a2c..0000000000
--- a/src/soc/amd/stoneyridge/smi_util.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * SMM utilities used in both SMM and normal mode
- */
-
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <soc/southbridge.h>
-#include <soc/smi.h>
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/smi.h>
-
-void configure_smi(uint8_t smi_num, uint8_t mode)
-{
-	uint8_t reg32_offset, bit_offset;
-	uint32_t reg32;
-
-	if (smi_num >= NUMBER_SMITYPES) {
-		printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num);
-		return;
-	}
-
-	/* 16 sources per register, 2 bits per source; registers are 4 bytes */
-	reg32_offset = (smi_num / 16) * 4;
-	bit_offset = (smi_num % 16) * 2;
-
-	reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset);
-	reg32 &= ~(0x3 << (bit_offset));
-	reg32 |= (mode & 0x3) << bit_offset;
-	smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32);
-}
-
-/**
- * Configure generation of interrupts for given GEVENT pin
- *
- * @param gevent The GEVENT pin number. Valid values are 0 thru 23
- * @param mode The type of event this pin should generate. Note that only
- *	       SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events.
- * @param level SMI__SCI_LVL_LOW or SMI_SCI_LVL_HIGH
- */
-void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level)
-{
-	uint32_t reg32;
-	/* GEVENT pins range from [0:23] */
-	if (gevent >= SMI_GEVENTS) {
-		printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent);
-		return;
-	}
-
-	/* SMI0 source is GEVENT0 and so on */
-	configure_smi(gevent, mode);
-
-	/* And set set the trigger level */
-	reg32 = smi_read32(SMI_REG_SMITRIG0);
-	reg32 &= ~(1 << gevent);
-	reg32 |= (level & 0x1) << gevent;
-	smi_write32(SMI_REG_SMITRIG0, reg32);
-}
-
-/**
- * Configure generation of SCIs.
- */
-void configure_scimap(const struct sci_source *sci)
-{
-	uint32_t reg32;
-
-	/* GEVENT pins range */
-	if (sci->scimap >= SCIMAPS) {
-		printk(BIOS_WARNING, "BUG: Invalid SCIMAP: %u\n",
-			sci->scimap);
-		return;
-	}
-
-	/* GPEs range from [0:31] */
-	if (sci->gpe >= SCI_GPES) {
-		printk(BIOS_WARNING, "BUG: Invalid SCI GPE: %u\n", sci->gpe);
-		return;
-	}
-
-	printk(BIOS_DEBUG, "SCIMAP %u maps to GPE %u (active %s, %s trigger)\n",
-		sci->scimap, sci->gpe,
-		(!!sci->direction) ? "high" : "low",
-		(!!sci->level) ? "level" : "edge");
-
-	/* Map Gevent to SCI GPE# */
-	smi_write8(SMI_SCI_MAP(sci->scimap), sci->gpe);
-
-	/* Set the trigger direction (high/low) */
-	reg32 = smi_read32(SMI_SCI_TRIG);
-	reg32 &= ~(1 << sci->gpe);
-	reg32 |= !!sci->direction << sci->gpe;
-	smi_write32(SMI_SCI_TRIG, reg32);
-
-	/* Set the trigger level (edge/level) */
-	reg32 = smi_read32(SMI_SCI_LEVEL);
-	reg32 &= ~(1 << sci->gpe);
-	reg32 |= !!sci->level << sci->gpe;
-	smi_write32(SMI_SCI_LEVEL, reg32);
-}
-
-void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes)
-{
-	size_t i;
-
-	for (i = 0; i < num_gpes; i++)
-		configure_scimap(scis + i);
-}
-
-/** Disable events from given GEVENT pin */
-void disable_gevent_smi(uint8_t gevent)
-{
-	/* GEVENT pins range from [0:23] */
-	if (gevent > 23) {
-		printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent);
-		return;
-	}
-
-	/* SMI0 source is GEVENT0 and so on */
-	configure_smi(gevent, SMI_MODE_DISABLE);
-}
-
-uint16_t pm_acpi_smi_cmd_port(void)
-{
-	return pm_read16(PM_ACPI_SMI_CMD);
-}