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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-02-21 17:59:42 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-28 22:36:34 +0000 |
| commit | 54c80e1df16d356dc73030903daece5fcb50e7bc (patch) | |
| tree | f5bbe1e183ae867abb43a72b4519275f07420e7c /src/soc/amd/stoneyridge/tsc_freq.c | |
| parent | b6b5af11712b303dab085a5c7c11aa003d4842a8 (diff) | |
soc/amd/*/acpi: add comment about p_lvl[2,3]_lat FADT field usage
The latency values in the _CST package override the values in the
p_lvl2_lat and p_lvl3_lat FADT fields. In Picasso, Cezanne, Mendocino,
Phoenix and Glinda generate_cpu_entries generates the _CST packages for
each CPU device. The coreboot code for Stoneyridge doesn't generate _CST
packages for the CPU objects, but those are provided via the PSTATE SSDT
binaryPI generates and agesa_write_acpi_tables gets and adds to the ACPI
tables. The AGESA reference code also sets those two FADT entries to the
equivalents of ACPI_FADT_C2_NOT_SUPPORTED and ACPI_FADT_C3_NOT_SUPPORTED
so this also matches the AGESA behavior.
From the ACPI 6.4 spec: "Values provided by the _CST object override
P_LVLx values in P_BLK and P_LVLx_LAT values in the FADT."
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1116a3013576b18b6f521604d6b0a9d75b971e0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/tsc_freq.c')
0 files changed, 0 insertions, 0 deletions