diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-09 15:47:59 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-10 16:00:55 +0000 |
| commit | 3fe1ad1f26314e9926037e7b0025b65582a34a75 (patch) | |
| tree | 5d678b001514a79e9d3eaea5668989a449b88136 /src/soc/amd/stoneyridge/reset.c | |
| parent | 244cf7d3a6d8db2a2ea5541815a0bd4e564c8195 (diff) | |
soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.h
The register name and the name of one bit are slightly different, but
have the same functionality.
Change-Id: Ie49975bb43868cbb2dc986e66dc5b7291e70222f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48507
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/reset.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/reset.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 88050a6f1f..d609205028 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> +#include <cf9_reset.h> #include <reset.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> @@ -40,7 +41,7 @@ void do_cold_reset(void) /* De-assert and then assert all PwrGood signals on CF9 reset. */ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); - outb(RST_CMD | SYS_RST, SYS_RESET); + outb(RST_CPU | SYS_RST, RST_CNT); } void do_warm_reset(void) @@ -49,7 +50,7 @@ void do_warm_reset(void) clear_bios_reset(); /* Assert reset signals only. */ - outb(RST_CMD | SYS_RST, SYS_RESET); + outb(RST_CPU | SYS_RST, RST_CNT); } void do_board_reset(void) |