diff options
author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-09-13 17:24:53 -0600 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-27 15:56:55 +0000 |
commit | a7bfbbedd6059183c5126bbea248fe52176f6386 (patch) | |
tree | 418b2d7ea065488be41e8a11deb0d3fbdf5bacaf /src/soc/amd/stoneyridge/model_15_init.c | |
parent | dc194e2bc4e7421d760693702775b39784522bb3 (diff) |
amd/stoneyridge: Convert MP init to mp_init_with_smm
Change the Stoney Ridge SOC to a more modern method for setting up
the multiple cores.
Add a new cpu.c file for most of the processor initiliazation. Build
mp_ops with the necessary callbacks. Note also that this patch removes
cpu_bus_scan. Rather than manually find CPUs and add them to the
devicetree, allow this to be done automatically in the generic
mp_init.c file.
SMM information is left blank in mp_ops to avoid having mp_init.c
install a handler at this time. A later patch will add TSEG SMM
capabilities for the APU.
This patch also contains a hack to mask the behavior of AGESA which
configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost.
The hack immediately changes all WB variable MTRRs, on the BSP, to UC
so that all writes to memory space will make it to the DRAM.
BUG=b:66200075
Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/model_15_init.c')
-rw-r--r-- | src/soc/amd/stoneyridge/model_15_init.c | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c index e89671821d..c3e9bf52bd 100644 --- a/src/soc/amd/stoneyridge/model_15_init.c +++ b/src/soc/amd/stoneyridge/model_15_init.c @@ -22,7 +22,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/pae.h> #include <pc80/mc146818rtc.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> @@ -30,36 +29,46 @@ #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> +static void msr_rw_dram(unsigned int reg) +{ +#define RW_DRAM (MTRR_READ_MEM | MTRR_WRITE_MEM) +#define ALL_RW_DRAM ((RW_DRAM << 24) | (RW_DRAM << 16) | \ + (RW_DRAM << 8) | (RW_DRAM)) + + msr_t mtrr = rdmsr(reg); + mtrr.hi |= ALL_RW_DRAM; + mtrr.lo |= ALL_RW_DRAM; + wrmsr(reg, mtrr); +} + static void model_15_init(device_t dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); - u8 i; + int i; msr_t msr; - int msrno; disable_cache(); + /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - // BSP: make a0000-bffff UC, c0000-fffff WB - msr.lo = msr.hi = 0; - wrmsr(MTRR_FIX_16K_A0000, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(MTRR_FIX_64K_00000, msr); - wrmsr(MTRR_FIX_16K_80000, msr); - for (msrno = MTRR_FIX_4K_C0000 ; msrno <= MTRR_FIX_4K_F8000 ; msrno++) - wrmsr(msrno, msr); + /* Send all but A0000-BFFFF to DRAM */ + msr_rw_dram(MTRR_FIX_64K_00000); + msr_rw_dram(MTRR_FIX_16K_80000); + for (i = MTRR_FIX_4K_C0000 ; i <= MTRR_FIX_4K_F8000 ; i++) + msr_rw_dram(i); + /* Hide RdDram and WrDram bits, and clear Tom2ForceMemTypeWB */ msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_TOM2WB; msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - x86_mtrr_check(); x86_enable_cache(); /* zero the machine check error status registers */ @@ -68,9 +77,6 @@ static void model_15_init(device_t dev) for (i = 0 ; i < 6 ; i++) wrmsr(MCI_STATUS + (i * 4), msr); - /* Enable the local CPU APICs */ - setup_lapic(); - /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); |