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authorAngel Pons <th3fanbus@gmail.com>2020-10-29 21:18:14 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-24 11:43:07 +0000
commit5d7c3a4f013d650aab87a71e6468e89586846703 (patch)
tree225cc575bc233cbcec0736228babed2c3c778be8 /src/soc/amd/stoneyridge/mca.c
parent3d35756d5a9ea48284c6a997e45d01e196bb6e48 (diff)
nb/intel/haswell/northbridge.c: Correct DPR handling
DPR size is in MiB, but the range boundaries are expressed in KiB. In addition, DPR and TSEG use the same attributes, so unify both regions. Also improve a comment about DPR, since `is special` is uninformative. Change-Id: I4479483e17890b5a4c39165138fa1c5f8215bc84 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46987 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/mca.c')
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