diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-05 18:35:12 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-06-06 17:58:28 +0000 |
| commit | eceaa97b27b04a61dd5fb2e68e0f5ac1367a3c0f (patch) | |
| tree | f81cfe8575ac8b66216cec2487fccf7a501591af /src/soc/amd/stoneyridge/lpc.c | |
| parent | 251d305e73f76ca3b63654273f3b2bb3de775457 (diff) | |
soc/amd/stoneyridge: Rework SPI base address get/set
A subsequent patch will move the soc//stoneyridge LPC functionality to
a common directory. Prepare by reworking the SPI BAR configuration
function in southbridge.h. The SPI BAR is not a typical PCI BAR, and
is at D14F3xA0.
Change-Id: I73ddb4afaf9e67ca0522ecb6085b23c92fedc461
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32652
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/lpc.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/lpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 3ace1fdce6..1741e92e0c 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -146,7 +146,7 @@ static void lpc_set_resources(struct device *dev) /* Special case. The SpiRomEnable and other enables should STAY set. */ res = find_resource(dev, 2); spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); - spi_enable_bits &= SPI_PRESERVE_BITS; + spi_enable_bits &= SPI_BASE_ALIGNMENT - 1; pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits); |