diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-06-16 18:46:00 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-17 18:44:04 +0000 |
| commit | dac1f66c6c889962e355277570f9c36b747eec8a (patch) | |
| tree | 3b2550c102cf9effb5000a4c12cedcb98157dcc7 /src/soc/amd/stoneyridge/include | |
| parent | 8bca2b18bcb32d07a1be52dea0cee17567e4baec (diff) | |
soc/amd/stoneyridge: factor out AOAC offset defines
Factoring out those defines brings the Stoneyridge SoC code a bit more
in line with the Cezanne and Picasso SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifba7f13cc926ac28376233aa0bf317164ca9bbd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55588
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/aoac_defs.h | 18 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 12 |
2 files changed, 18 insertions, 12 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/aoac_defs.h b/src/soc/amd/stoneyridge/include/soc/aoac_defs.h new file mode 100644 index 0000000000..26dbd27999 --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/aoac_defs.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_STONEYRIDGE_AOAC_DEFS_H +#define AMD_STONEYRIDGE_AOAC_DEFS_H + +/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C0 5 +#define FCH_AOAC_DEV_I2C1 6 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_USB2 18 +#define FCH_AOAC_DEV_USB3 23 + +#endif /* AMD_STONEYRIDGE_AOAC_DEFS_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 80a6c6bc58..224010c24d 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -131,18 +131,6 @@ #define DEBUG_PORT_ENABLE BIT(18) #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) -/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ -#define FCH_AOAC_DEV_CLK_GEN 0 -#define FCH_AOAC_DEV_I2C0 5 -#define FCH_AOAC_DEV_I2C1 6 -#define FCH_AOAC_DEV_I2C2 7 -#define FCH_AOAC_DEV_I2C3 8 -#define FCH_AOAC_DEV_UART0 11 -#define FCH_AOAC_DEV_UART1 12 -#define FCH_AOAC_DEV_AMBA 17 -#define FCH_AOAC_DEV_USB2 18 -#define FCH_AOAC_DEV_USB3 23 - #define PM1_LIMIT 16 #define GPE0_LIMIT 28 #define TOTAL_BITS(a) (8 * sizeof(a)) |