diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-09-27 08:31:02 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-01 14:32:17 +0000 |
| commit | d61e347bffae29e6db179641652602226711e401 (patch) | |
| tree | 8781df30c45ff2eeebbc527b1658adc0311f931c /src/soc/amd/stoneyridge/include | |
| parent | fc458cdc5374a293483455acdd42cdbdd032ae27 (diff) | |
amd/stoneyridge: Add USB settings to gnvs
A later patch will rely on two USB settings from the BIOS. Add these
to the global_gnvs_t structure.
The first is a data that will be used to locate the xHCI firmware for
reloading after a resume. Although the existing calculations will be
somewhat simple, keeping this on the coreboot side will help in the
event multiple FWs are eventually in the build.
The second item is a usable EHCI base address that may be programmed
during S3 suspend and resume. At the time the PTS and WAK code runs,
the BAR will be clear.
BUG=b:77602074
Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/nvs.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index dfc10a2e25..1477358a24 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -53,7 +53,12 @@ typedef struct global_nvs_t { uint8_t tmax; /* 0x30 - CPU Tj_max */ uint8_t pad1[3]; aoac_devs_t aoac; /* 0x34 - AOAC device enables */ - uint8_t unused[200]; + uint16_t fw00; /* 0x38 - XhciFwRomAddr_Rom, Boot RAM */ + uint16_t fw02; /* 0x3A - XhciFwRomAddr_Ram, Instr RAM */ + uint32_t fw01; /* 0x3C - XhciFwRamAddr_Rom, Boot RAM sz/base */ + uint32_t fw03; /* 0x40 - XhciFwRomAddr_Ram, Instr RAM sz/base */ + uint32_t eh10; /* 0x40 - EHCI BAR */ + uint8_t unused[184]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; |