diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-11-26 22:47:43 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-30 21:56:00 +0000 |
| commit | 54888d0846c5cb22fdadb81238a9aafc100b79fc (patch) | |
| tree | a0f0fec7c0339503b939d2ff4b1928215d859db0 /src/soc/amd/stoneyridge/include | |
| parent | b63e1f114b7f2a06c4f5087a46f18cdf67cb4d50 (diff) | |
soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1
Despite Stoneyridge being one only SoC in soc/amd that uses the first
generation of the PSP mailblox interface, this code is common for all
SoCs that use the first PSP mailbox interface generation, so move it to
the common PSP generation 1 code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59701
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 97eb806682..74e949809d 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -181,7 +181,6 @@ void soc_enable_psp_early(void); #define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */ -#define PSP_MAILBOX_OFFSET 0x70 /* offset from BAR3 value */ #define PSP_BAR_ENABLES 0x48 #define BAR3HIDE BIT(12) /* Bit to hide BAR3 addr */ |