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authorFelix Held <felix-coreboot@felixheld.de>2023-03-09 14:42:54 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-03-27 12:03:18 +0000
commit25b5982d107b48642036c19c495364b72fed71ff (patch)
tree0cd2ceaefd7ee2524fe559df03382f37f38f2de9 /src/soc/amd/stoneyridge/include
parentca8a8de999824bfae5b66b32a237246805ed857c (diff)
soc/amd/stoneyridge/include/msr: add pstate_msr bitfield struct
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs which will be used in future patches to generate the P state ACPI packages for the CPU objects. BKDG #55072 Rev 3.04 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I944c8598ba95a0333124655c61ef9eba8a7595c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73998 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/msr.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/msr.h b/src/soc/amd/stoneyridge/include/soc/msr.h
new file mode 100644
index 0000000000..d3c537ca28
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/msr.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_STONEYRIDGE_MSR_H
+#define AMD_STONEYRIDGE_MSR_H
+
+/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
+union pstate_msr {
+ struct {
+ uint64_t cpu_fid_0_5 : 6; /* [ 0.. 5] */
+ uint64_t cpu_dfs_id : 3; /* [ 6.. 8] */
+ uint64_t cpu_vid_0_7 : 8; /* [ 9..16] */
+ uint64_t : 5; /* [17..21] */
+ uint64_t nb_pstate : 1; /* [22..22] */
+ uint64_t : 9; /* [23..31] */
+ uint64_t idd_value : 8; /* [32..39] */
+ uint64_t idd_div : 2; /* [40..41] */
+ uint64_t : 21; /* [42..62] */
+ uint64_t pstate_en : 1; /* [63..63] */
+ };
+ uint64_t raw;
+};
+
+#endif /* AMD_STONEYRIDGE_MSR_H */