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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-03-15 15:45:44 -0700
committerMartin Roth <martinroth@google.com>2018-03-19 14:19:46 +0000
commit6dfbb593077ea3edb9162431c2380a268d35fc4a (patch)
treeaf60b48533a4a0c07140d42e96d8c561c152163a /src/soc/amd/stoneyridge/include
parent6bff3bf4be7fd94e6ffd080e498bbe75c75418d9 (diff)
soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uart
The GPIO programming of configure_stoneyridge_UART() can be done by the early GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart() became redundant. Remove procedure configure_stoneyridge_uart(). BUG=b:74258015 TEST=Build and boot kahlee, observing serial output does not changes from previous serial output. Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25192 Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 6dea0c6864..bdcb38fa8d 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -353,7 +353,6 @@ struct stoneyridge_aoac {
void enable_aoac_devices(void);
void sb_enable_rom(void);
-void configure_stoneyridge_uart(void);
void configure_stoneyridge_i2c(void);
void sb_clk_output_48Mhz(void);
void sb_disable_4dw_burst(void);