diff options
author | Felix Held <felix-coreboot@felixheld.de> | 2021-12-15 20:52:10 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-20 17:38:12 +0000 |
commit | 25aa5606c26fe5ac5a5d287245aa860e8b99d2cb (patch) | |
tree | 7cfa4d48bd0b5453f0734ff3ec0266a07fec4177 /src/soc/amd/stoneyridge/fch_agesa.c | |
parent | fbfb906081f9eb5b1d94346b27f4d33ab37e45ec (diff) |
soc/amd/stoneyridge: factor out AGESA-wrapper related FCH functions
Split the code that gets called from the AGESA wrapper from the rest of
the FCH/southbridge code that directly interacts with the hardware.
Since the remaining parts of southbridge.c aren't used in romstage,
drop it from the list of build targets for romstage.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6197add0e1396a82545735653110e1e17bf9c303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/fch_agesa.c')
-rw-r--r-- | src/soc/amd/stoneyridge/fch_agesa.c | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/fch_agesa.c b/src/soc/amd/stoneyridge/fch_agesa.c new file mode 100644 index 0000000000..ee6ab91c6d --- /dev/null +++ b/src/soc/amd/stoneyridge/fch_agesa.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/agesawrapper.h> +#include <device/device.h> +#include <soc/pci_devs.h> + +static int is_sata_config(void) +{ + return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) + || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE)); +} + +static inline int sb_sata_enable(void) +{ + /* True if IDE or AHCI. */ + return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || + (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE); +} + +static inline int sb_ide_enable(void) +{ + /* True if IDE or LEGACY IDE. */ + return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || + (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE); +} + +void SetFchResetParams(FCH_RESET_INTERFACE *params) +{ + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); + params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); + if (dev && dev->enabled) { + params->SataEnable = sb_sata_enable(); + params->IdeEnable = sb_ide_enable(); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + } +} + +void SetFchEnvParams(FCH_INTERFACE *params) +{ + const struct device *dev = pcidev_path_on_root(SATA_DEVFN); + params->AzaliaController = AzEnable; + params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; + if (dev && dev->enabled) { + params->SataEnable = is_sata_config(); + params->IdeEnable = !params->SataEnable; + params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == + SataLegacyIde); + } else { + params->SataEnable = FALSE; + params->IdeEnable = FALSE; + params->SataIdeMode = FALSE; + } +} + +void SetFchMidParams(FCH_INTERFACE *params) +{ + SetFchEnvParams(params); +} |