diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-01-20 19:56:30 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-05-21 14:41:03 +0000 |
| commit | b768723c72b326b24703a8e67764c995711050d9 (patch) | |
| tree | 4e4e6d5de4f6e5c04aee3f599bce1e82c725ff1b /src/soc/amd/stoneyridge/cpu.c | |
| parent | 368873ced315fb00b1052b5e5633d2d157a8f0a1 (diff) | |
soc/amd/picasso: Add APOB NV back for non-S3
New information indicates the PSP expects the APOB NV region
populated for all types of boot, and this is not a feature only
used for S3. Switch over to using the MRC_CACHE flash region.
Remove the Kconfig symbols for the APOB_NV base and size. Override
the MRC_CACHE_SETTINGS_CACHE_SIZE to ensure the default maintains the
minimum required size. Use the generated (or mainboard-specified)
fmap.fmd file as an input for amdfwtool and properly match the
flash region.
Change the original naming for the APOB destination, which matched the
PSP spec's field name, to PSP_APOB_DESTINATION. This should be more
intuitive for a source code reader. The APOB address is the location
in DRAM where the PSP puts its output block.
BUG=b:147042464, b:153675914
TEST=Boot trembyle
Original-Change-Id: Ia5ba8646deec2bd282df930f471738723063eef8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080375
Original-Change-Id: I972d66f1817f86ff0b689f011c0c44c3fe7c8ef7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2053312
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I4550766ece462b65a6bfe6f1b747343e08e53fe5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/cpu.c')
0 files changed, 0 insertions, 0 deletions