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authorDuncan Laurie <dlaurie@google.com>2018-05-07 15:37:28 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-05-18 12:23:17 +0000
commit32bdffaf54700bce12b3a9a3e232c2274ebf56f1 (patch)
tree65dfd01526dd49b05dab93e8618069e582ced3bf /src/soc/amd/stoneyridge/acpi/usb.asl
parentbf713b04b6f04ebf91eea40867a5354c958182f4 (diff)
soc/amd/stoneyridge: Support ACPI USB code generation
To support generating USB devices in ACPI the platform needs to know how to determine a device name for each USB port, and for any root hubs that may be present. The AMD Stoney Ridge platform has separate controllers for USB 2.0 and USB 3.0. The USB 2.0 ports are connected through a hub to an EHCI controller while the USB 3.0 ports are directly connected to the xHCI controller. This topology is described in ACPI and the port names are exposed by the soc_acpi_name() function. The USB controllers are configured to scan for static USB devices in the devicetree and use the soc_acpi_name() function to identify them. Change-Id: I2bb677f84a49d2531929985dba319455b88e1686 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi/usb.asl')
-rw-r--r--src/soc/amd/stoneyridge/acpi/usb.asl14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/usb.asl b/src/soc/amd/stoneyridge/acpi/usb.asl
index 3fd76b22dd..6c6ff9c9d0 100644
--- a/src/soc/amd/stoneyridge/acpi/usb.asl
+++ b/src/soc/amd/stoneyridge/acpi/usb.asl
@@ -17,10 +17,24 @@
/* 0:12.0 - EHCI */
Device(EHC0) {
Name(_ADR, 0x00120000)
+ Device (RHUB) {
+ Name (_ADR, Zero)
+ Device (HS01) { Name (_ADR, 1) }
+ Device (HS02) { Name (_ADR, 2) }
+ Device (HS03) { Name (_ADR, 3) }
+ Device (HS04) { Name (_ADR, 4) }
+ Device (HS05) { Name (_ADR, 5) }
+ Device (HS06) { Name (_ADR, 6) }
+ Device (HS07) { Name (_ADR, 7) }
+ Device (HS08) { Name (_ADR, 8) }
+ }
} /* end EHC0 */
/* 0:10.0 - XHCI 0*/
Device(XHC0) {
Name(_ADR, 0x00100000)
+ Device (SS01) { Name (_ADR, 1) }
+ Device (SS02) { Name (_ADR, 2) }
+ Device (SS03) { Name (_ADR, 3) }
} /* end XHC0 */