diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-01 22:06:53 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 00:29:39 +0000 |
| commit | f6421311c96fd3ffef0e9b4791c9c25a2f03d055 (patch) | |
| tree | a6a0c62ffece241565facbd8278fe5d6687fb28c /src/soc/amd/stoneyridge/acpi/soc.asl | |
| parent | 4d6c39d4f41b4d7dbfbb1df04390ccafbc487b42 (diff) | |
soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro
Instead of having the different static parts of the PCI0 device in
northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the
PCI0 device via the ROOT_BRIDGE macro in soc.asl.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a9af2fd853f4e993e71158c5e85052084b50cdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75596
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi/soc.asl')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/soc.asl | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl index b411c20ba4..47d5992272 100644 --- a/src/soc/amd/stoneyridge/acpi/soc.asl +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device(PCI0) { +#include <soc/amd/common/acpi/pci_root.asl> + +ROOT_BRIDGE(PCI0) + +Scope(PCI0) { /* Describe the AMD Northbridge */ #include "northbridge.asl" |