diff options
| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-05-16 12:09:37 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-06-12 21:15:16 +0000 |
| commit | 9b05af367fde33fc620c4cd759c2b09cdc036cc9 (patch) | |
| tree | 61fce7ebb6e70b88d978ee112e8575d70557eb3d /src/soc/amd/stoneyridge/acpi/soc.asl | |
| parent | 29cc33181a18e76d033a4f8dc5d3bbd982ce4b9b (diff) | |
soc/amd/stoneyridge/acpi: Create a GPIO library
There are some acpigen functionality that have not been implemented. In
order to implement them, ACPI GPIO functions to read and write to the
control MMIO of a particular pin is needed. So as a preliminary task to
implementing acpigen functions, create a library with functions to be
accessed by acpigen generated ACPI code.
BUG=b:79546790
TEST=Build grunt, more tests with commit 0f2acbd6b1.
Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/acpi/soc.asl')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/soc.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl index d7772948ef..6fd838a56d 100644 --- a/src/soc/amd/stoneyridge/acpi/soc.asl +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -26,3 +26,6 @@ Device(PCI0) { /* Describe the devices in the Southbridge */ #include "sb_fch.asl" + +/* Add GPIO library */ +#include <gpio_lib.asl> |