diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-06-21 17:37:18 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-27 20:51:55 +0000 |
| commit | 6a9f846bcdfd35c9c2a552ef3879f6fd14b08fd5 (patch) | |
| tree | 7a284f02506ffd2ad122274979db18ea2ff13693 /src/soc/amd/stoneyridge/Makefile.inc | |
| parent | 8a906dff84950c0789afc05e046a377846f7f6ea (diff) | |
soc/stoneyridge: Remove FCH PCIe support
Remove the pcie.c file. Historically PCIe lanes have been
available from the Gfx and/or the FCH. The integrated FCH in
this APU has no PCIe available.
BUG=chrome-os-partner:62580062
Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/amd/stoneyridge/Makefile.inc')
| -rw-r--r-- | src/soc/amd/stoneyridge/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index bc128a13d1..59fbbbe0f1 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -59,7 +59,6 @@ ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c ramstage-y += lpc.c ramstage-y += model_15_init.c ramstage-y += northbridge.c -ramstage-y += pcie.c ramstage-y += reset.c ramstage-y += sata.c ramstage-y += sd.c |