From 6a9f846bcdfd35c9c2a552ef3879f6fd14b08fd5 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 21 Jun 2017 17:37:18 -0600 Subject: soc/stoneyridge: Remove FCH PCIe support Remove the pcie.c file. Historically PCIe lanes have been available from the Gfx and/or the FCH. The integrated FCH in this APU has no PCIe available. BUG=chrome-os-partner:62580062 Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/20319 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Stefan Reinauer --- src/soc/amd/stoneyridge/Makefile.inc | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/amd/stoneyridge/Makefile.inc') diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index bc128a13d1..59fbbbe0f1 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -59,7 +59,6 @@ ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c ramstage-y += lpc.c ramstage-y += model_15_init.c ramstage-y += northbridge.c -ramstage-y += pcie.c ramstage-y += reset.c ramstage-y += sata.c ramstage-y += sd.c -- cgit v1.2.3