soc/amd/sabrina: Add support for Rembrandt SoC as base SoC

This change adds new Rembrandt SoC support by defining it as base SoC
of sabrina as sabrina is derived from Rembrandt SoC.
All the needed changes for Rembrandt SoC will be applied under
SOC_AMD_REMBRANDT config.

Change-Id: I1c9392918cc2c6b511d467f99aceefc725750ce6
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

3 files changed, 110 insertions, 4 deletions

diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index e6a9875b3e..2e9022f24c 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -2,12 +2,23 @@
 
 # TODO: Check if this is still correct
 
+config SOC_AMD_REMBRANDT_BASE
+	bool
+
 config SOC_AMD_SABRINA
 	bool
+	select SOC_AMD_REMBRANDT_BASE
 	help
 	  AMD Sabrina support
 
-if SOC_AMD_SABRINA
+config SOC_AMD_REMBRANDT
+	bool
+	select SOC_AMD_REMBRANDT_BASE
+	help
+	  AMD Rembrandt support
+
+
+if SOC_AMD_REMBRANDT_BASE
 
 config SOC_SPECIFIC_OPTIONS
 	def_bool y
@@ -88,7 +99,8 @@ config ARCH_ALL_STAGES_X86
 
 config CHIPSET_DEVICETREE
 	string
-	default "soc/amd/sabrina/chipset.cb"
+	default "soc/amd/sabrina/chipset_sabrina.cb" if SOC_AMD_SABRINA
+	default "soc/amd/sabrina/chipset_rembrandt.cb"
 
 config EARLY_RESERVED_DRAM_BASE
 	hex
@@ -231,7 +243,8 @@ config ECAM_MMCONF_BUS_NUMBER
 
 config MAX_CPUS
 	int
-	default 8
+	default 8 if SOC_AMD_SABRINA
+	default 16
 	help
 	  Maximum number of threads the platform can have.
 
@@ -489,4 +502,4 @@ config RWB_REGION_ONLY
 
 endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
 
-endif # SOC_AMD_SABRINA
+endif # SOC_AMD_REMBRANDT_BASE
diff --git a/src/soc/amd/sabrina/chipset_rembrandt.cb b/src/soc/amd/sabrina/chipset_rembrandt.cb
new file mode 100644
index 0000000000..ecb1da6ba1
--- /dev/null
+++ b/src/soc/amd/sabrina/chipset_rembrandt.cb
@@ -0,0 +1,93 @@
+chip soc/amd/rembrandt
+	device cpu_cluster 0 on
+	end
+	device domain 0 on
+		device pci 00.0 alias gnb on end
+		device pci 00.2 alias iommu off end
+
+		device pci 01.0 on end # Dummy Host Bridge
+
+		device pci 02.0 on end # Dummy Host Bridge, do not disable
+		device pci 02.1 alias gpp_bridge_0 off end
+		device pci 02.2 alias gpp_bridge_1 off end
+		device pci 02.3 alias gpp_bridge_2 off end
+		device pci 02.4 alias gpp_bridge_3 off end
+		device pci 02.5 alias gpp_bridge_4 off end
+		device pci 02.6 alias gpp_bridge_5 off end
+
+		device pci 08.0 on end # Dummy Host Bridge, do not disable
+		device pci 08.1 alias gpp_bridge_a off  # Internal GPP Bridge 0 to Bus A
+			device pci 0.0 alias gfx off end # Internal GPU (GFX)
+			device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
+			device pci 0.2 alias crypto off end # Crypto Coprocessor
+			device pci 0.3 alias xhci_0 off
+				chip drivers/usb/acpi
+					register "type" = "UPC_TYPE_HUB"
+					device usb 0.0 alias xhci_0_root_hub off
+						chip drivers/usb/acpi
+							device usb 3.0 alias usb3_port0 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.0 alias usb2_port0 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.1 alias usb2_port1 off end
+						end
+					end
+				end
+			end
+			device pci 0.4 alias xhci_1 off
+				chip drivers/usb/acpi
+					register "type" = "UPC_TYPE_HUB"
+					device usb 0.0 alias xhci_1_root_hub off
+						chip drivers/usb/acpi
+							device usb 3.0 alias usb3_port2 off end
+						end
+						chip drivers/usb/acpi
+							device usb 3.1 alias usb3_port3 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.0 alias usb2_port2 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.1 alias usb2_port3 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.2 alias usb2_port4 off end
+						end
+					end
+				end
+			end
+			device pci 0.5 alias acp off end # Audio Processor (ACP)
+			device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
+			device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
+		end
+		device pci 08.2 alias gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B
+		device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+			device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID
+		end
+
+		device pci 14.0 alias smbus on end # primary FCH function
+		device pci 14.3 alias lpc_bridge on end
+
+		device pci 18.0 alias data_fabric_0 on end
+		device pci 18.1 alias data_fabric_1 on end
+		device pci 18.2 alias data_fabric_2 on end
+		device pci 18.3 alias data_fabric_3 on end
+		device pci 18.4 alias data_fabric_4 on end
+		device pci 18.5 alias data_fabric_5 on end
+		device pci 18.6 alias data_fabric_6 on end
+		device pci 18.7 alias data_fabric_7 on end
+	end
+
+	device mmio 0xfedc2000 alias i2c_0 off end
+	device mmio 0xfedc3000 alias i2c_1 off end
+	device mmio 0xfedc4000 alias i2c_2 off end
+	device mmio 0xfedc5000 alias i2c_3 off end
+	device mmio 0xfedc9000 alias uart_0 off end
+	device mmio 0xfedca000 alias uart_1 off end
+	device mmio 0xfedce000 alias uart_2 off end
+	device mmio 0xfedcf000 alias uart_3 off end
+	device mmio 0xfedd1000 alias uart_4 off end
+	device mmio 0xfedd5000 alias emmc off end
+end
diff --git a/src/soc/amd/sabrina/chipset.cb b/src/soc/amd/sabrina/chipset_sabrina.cb
index bd5a60daab..bd5a60daab 100644
--- a/src/soc/amd/sabrina/chipset.cb
+++ b/src/soc/amd/sabrina/chipset_sabrina.cb