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author | Krystian Hebel <krystian.hebel@3mdeb.com> | 2020-09-23 14:40:45 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-11 13:54:26 +0000 |
commit | e527c713bd3533858054fe389ec2a5c93f6d6726 (patch) | |
tree | 0c188b15f4d0dcf9a75e054d1db1eed9a51b775f /src/soc/amd/sabrina/gpio.c | |
parent | 707e5452e7037bfc918862901401608469d2e86a (diff) |
ppc64/bootblock_crt0.S: minimal implementation for bootblock C environment
BSS is loaded as part of the bootblock, it is zeroed in the file so it
doesn't have to be cleared explicitly by the code.
Code for clearing is left as a comment along with a warning about alignment
requirements.
Vector operations are sometimes generated for code such as
'uint8_t x[32] = {0}', this results in an exception when vector registers
(VR) are not enabled. VSR (vector-scalar register) operations are also
enabled, there is no reason not to.
Change-Id: I878ef61619eb4a191805c8911d001312a0d717a0
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/soc/amd/sabrina/gpio.c')
0 files changed, 0 insertions, 0 deletions