soc/amd/sabrina: only make the available clock outputs configurable

Sabrina only has 4 PCIe clock outputs with corresponding clock request
pins available, so only make those 4 configurable in devicetree and
disable the rest unconditionally.

TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

1 files changed, 4 insertions, 2 deletions

diff --git a/src/soc/amd/sabrina/fch.c b/src/soc/amd/sabrina/fch.c
index a768989b64..533eb9489c 100644
--- a/src/soc/amd/sabrina/fch.c
+++ b/src/soc/amd/sabrina/fch.c
@@ -151,9 +151,11 @@ static void gpp_clk_setup(void)
 		 * The remapping of values is done so that the default of the enum used for the
 		 * devicetree settings is the clock being enabled, so that a missing devicetree
 		 * configuration for this will result in an always active clock and not an
-		 * inactive PCIe clock output.
+		 * inactive PCIe clock output. Only the configuration for the clock outputs
+		 * available on the package is provided via the devicetree; the rest is
+		 * switched off unconditionally.
 		 */
-		switch (cfg->gpp_clk_config[i]) {
+		switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) {
 		case GPP_CLK_REQ:
 			gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
 			break;