diff options
author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-19 22:06:11 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-27 23:03:43 +0000 |
commit | ba21a1f76c363f752b82c569b787bfde3337535e (patch) | |
tree | 1c5fd71bc444b55f60144fe74bb8fe605b43e279 /src/soc/amd/sabrina/espi_util.c | |
parent | cbf290c692b254badb091506cc11855b52ddf266 (diff) |
soc/amd/sabrina: drop PM_ESPI_CS_USE_DATA2 define and eSPI util code
The Sabrina SoC doesn't have the PM_ESPI_CS_USE_DATA2 bit defined in the
PM_SPI_PAD_PU_PD register. It also doesn't have a physical LPC interface
any more, so there are no LPC pins that can be reconfigured as eSPI
interface.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I02bc8d007901c71942475fe707637c5da7227230
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/sabrina/espi_util.c')
-rw-r--r-- | src/soc/amd/sabrina/espi_util.c | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/src/soc/amd/sabrina/espi_util.c b/src/soc/amd/sabrina/espi_util.c deleted file mode 100644 index 41289aeb26..0000000000 --- a/src/soc/amd/sabrina/espi_util.c +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Check if this is still correct */ - -#include <amdblocks/acpimmio.h> -#include <amdblocks/lpc.h> -#include <device/pci_ops.h> -#include <soc/espi.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/southbridge.h> -#include <types.h> - -void espi_disable_lpc_ldrq(void) -{ - /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped - on Picasso and older compared to Renoir/Cezanne and newer */ - uint32_t dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); - dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); - dword |= LPC_LDRQ0_PD_EN; - pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); -} - -void espi_switch_to_spi2_pads(void) -{ - /* Use SPI2 pins for eSPI */ - uint32_t dword = pm_read32(PM_SPI_PAD_PU_PD); - dword |= PM_ESPI_CS_USE_DATA2; - pm_write32(PM_SPI_PAD_PU_PD, dword); - - /* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */ - dword = pm_read32(PM_ACPI_CONF); - dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; - pm_write32(PM_ACPI_CONF, dword); -} |