soc/amd/sabrina: add new SoC as copy of soc/amd/cezanne

The Cezanne SoC code was initially started as a copy of example/min86
which only provides enough code to make the SoC code build. Then the
different parts of the real SoC support was brought in patch by patch
which also helped cleaning up and untangling the code. Since the Cezanne
SoC code is now in a rather good shape and the Sabrina SoC is similar to
the Cezanne SoC from the coreboot side, the new SoC support is started
with a copy of the Cezanne code and all the needed changes will be
applied on top of that. In order for the build not to fail due to
duplicate files, this patch does not only copy the directory, but also
replaces most instances of the Cezanne name with Sabrina. Since the
needed blobs aren't available in the 3rdparty/amd_blobs repository yet,
the Cezanne blobs are used for now so that the build will succeed. As
soon as the proper blobs will be available in that repository, the code
will be switched over to use them.

As suggested by Nico, I added a "TODO: Check if this is still correct"
comment to the beginning of every copied file and all SOC_AMD_COMMON_*
Kconfig option selects which will be removed after re-verifying that
each file and each selected common code block is still correct for the
new SoC.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

1 files changed, 35 insertions, 0 deletions

diff --git a/src/soc/amd/sabrina/espi_util.c b/src/soc/amd/sabrina/espi_util.c
new file mode 100644
index 0000000000..41289aeb26
--- /dev/null
+++ b/src/soc/amd/sabrina/espi_util.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* TODO: Check if this is still correct */
+
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/lpc.h>
+#include <device/pci_ops.h>
+#include <soc/espi.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/southbridge.h>
+#include <types.h>
+
+void espi_disable_lpc_ldrq(void)
+{
+	/* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped
+	   on Picasso and older compared to Renoir/Cezanne and newer */
+	uint32_t dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS);
+	dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN);
+	dword |= LPC_LDRQ0_PD_EN;
+	pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword);
+}
+
+void espi_switch_to_spi2_pads(void)
+{
+	/* Use SPI2 pins for eSPI */
+	uint32_t dword = pm_read32(PM_SPI_PAD_PU_PD);
+	dword |= PM_ESPI_CS_USE_DATA2;
+	pm_write32(PM_SPI_PAD_PU_PD, dword);
+
+	/* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */
+	dword = pm_read32(PM_ACPI_CONF);
+	dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL;
+	pm_write32(PM_ACPI_CONF, dword);
+}