diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-12 23:18:54 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-27 22:18:17 +0000 |
| commit | b1fe9de74d420cf7193135c2b6d034bf06dabe94 (patch) | |
| tree | 414d6251c4e22441c9b7a9bf2967f7ba84131efa /src/soc/amd/sabrina/chip.c | |
| parent | a48f29192dd01e3be490394b265b90b619e81d4a (diff) | |
soc/amd/sabrina: add additional UART controllers
Compared to Cezanne there are 3 more UART controllers. Revision 1.50 of
the PPR #57243 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I628b1a7a0930f3409acdcabda2b864d42bf6bd23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Diffstat (limited to 'src/soc/amd/sabrina/chip.c')
| -rw-r--r-- | src/soc/amd/sabrina/chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/sabrina/chip.c b/src/soc/amd/sabrina/chip.c index 9835c6ed42..c00f91b55d 100644 --- a/src/soc/amd/sabrina/chip.c +++ b/src/soc/amd/sabrina/chip.c @@ -59,6 +59,9 @@ static void set_mmio_dev_ops(struct device *dev) break; case APU_UART0_BASE: case APU_UART1_BASE: + case APU_UART2_BASE: + case APU_UART3_BASE: + case APU_UART4_BASE: dev->ops = &sabrina_uart_mmio_ops; break; case APU_EMMC_BASE: |