diff options
| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2020-02-14 18:24:54 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-05-18 19:28:08 +0000 |
| commit | ed03371e76239dae16b6397efef4814f8c30451e (patch) | |
| tree | 54da98e758d1d6d89c569ba9187004c6db0923ac /src/soc/amd/picasso | |
| parent | 15fd30f0407f64684c975405888534dbd4be5ebf (diff) | |
soc/amd/picasso: add telemetry setting
Add telemetry setting for SDLE testing
BUG=b:147570294
TEST=Build Morphius and check the setting was been applied
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If4bb75eeaaa68b2c5a6a36c28c34fb338be65851
Reviewed-on: https://chromium-review.googlesource.com/2056885
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 8d4e0d3875..80cb1ceab2 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -72,6 +72,10 @@ struct soc_amd_picasso_config { uint8_t core_dldo_bypass; uint8_t min_soc_vid_offset; uint8_t aclk_dpm0_freq_400MHz; + uint32_t telemetry_vddcr_vdd_slope; + uint32_t telemetry_vddcr_vdd_offset; + uint32_t telemetry_vddcr_soc_slope; + uint32_t telemetry_vddcr_soc_offset; enum { SD_EMMC_DISABLE, diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index f038456b29..e6bc5c9c8f 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -74,6 +74,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->core_dldo_bypass = config->core_dldo_bypass; mcfg->min_soc_vid_offset = config->min_soc_vid_offset; mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz; + mcfg->telemetry_vddcr_vdd_slope = config->telemetry_vddcr_vdd_slope; + mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset; + mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope; + mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset; } asmlinkage void car_stage_entry(void) |