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authorRaul E Rangel <rrangel@chromium.org>2021-02-18 16:50:47 -0700
committerPatrick Georgi <pgeorgi@google.com>2021-02-22 07:29:41 +0000
commitd75ee46d3ce6f5f11d3a39752c8f48b713c1aa6a (patch)
treed3324d541b3c9730547631d8925b1ebca043ced4 /src/soc/amd/picasso
parent0b123dd72e82eaa90b3682cd13b57a88e634c53e (diff)
soc/amd/picasso/acpi: Change PCI0 BAR window
Picasso currently declares the BAR region between TOM and IO_APIC_ADDR. This region includes MMCONF. We don't want to map any PCI BARs in this region. This also matches what intel does. See soc/intel/braswell/acpi/southcluster.asl for an example. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso')
-rw-r--r--src/soc/amd/picasso/acpi/sb_pci0_fch.asl4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
index ed321f3e32..0b253c9cdc 100644
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
@@ -73,9 +73,9 @@ Method(_CRS, 0) {
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
- /* Declare memory between TOM1 and IOAPIC as available for PCI MMIO. */
+ /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
MM1B = TOM1
- Local0 = IO_APIC_ADDR /* This is the first MMIO device after TOM1. */
+ Local0 = CONFIG_MMCONF_BASE_ADDRESS
Local0 -= TOM1
MM1L = Local0