soc/amd/picasso: Introduce enums for SPI read mode and speed

This change adds enums for spi_read_mode and spi100_speed in
preparation for adding these to chip.h in follow-up CLs. This makes it
easier to reference what the mainboard is expected to set for these
SPI configs.

BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that SPI configuration is correct for trembyle.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7f9778b41bd059a50f20993415ebd8702a1ad58e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40823
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 41 insertions, 26 deletions

diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index cf1d124744..1ce7019526 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -243,15 +243,25 @@
 
 #define SPI_CNTRL0			0x00
 #define   SPI_BUSY			BIT(31)
+enum spi_read_mode {
+	SPI_READ_MODE_NORMAL33M = 0,
+	/* 1 is reserved. */
+	SPI_READ_MODE_DUAL112 = 2,
+	SPI_READ_MODE_QUAD114 = 3,
+	SPI_READ_MODE_DUAL122 = 4,
+	SPI_READ_MODE_QUAD144 = 5,
+	SPI_READ_MODE_NORMAL66M = 6,
+	SPI_READ_MODE_FAST_READ = 7,
+};
+/*
+ * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for
+ * SpiReadMode.
+ */
 #define   SPI_READ_MODE_MASK		(BIT(30) | BIT(29) | BIT(18))
-/* Nominal is 16.7MHz on older devices, 33MHz on newer */
-#define   SPI_READ_MODE_NOM		0x00000000
-#define   SPI_READ_MODE_DUAL112		(          BIT(29)          )
-#define   SPI_READ_MODE_QUAD114		(          BIT(29) | BIT(18))
-#define   SPI_READ_MODE_DUAL122		(BIT(30)                    )
-#define   SPI_READ_MODE_QUAD144		(BIT(30) |           BIT(18))
-#define   SPI_READ_MODE_NORMAL66	(BIT(30) | BIT(29)          )
-#define   SPI_READ_MODE_FAST		(BIT(30) | BIT(29) | BIT(18))
+#define   SPI_READ_MODE_UPPER_BITS(x)	((((x) >> 1) & 0x3) << 29)
+#define   SPI_READ_MODE_LOWER_BITS(x)	(((x) & 0x1) << 18)
+#define   SPI_READ_MODE(x)		(SPI_READ_MODE_UPPER_BITS(x) | \
+					 SPI_READ_MODE_LOWER_BITS(x))
 #define   SPI_ACCESS_MAC_ROM_EN		BIT(22)
 #define   SPI_FIFO_PTR_CLR		BIT(20)
 #define   SPI_ARB_ENABLE		BIT(19)
@@ -264,16 +274,24 @@
 
 /* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
 #define SPI100_SPEED_CONFIG		0x22
-#define   SPI_SPEED_66M			(0x0)
-#define   SPI_SPEED_33M			(                  BIT(0))
-#define   SPI_SPEED_22M			(         BIT(1)         )
-#define   SPI_SPEED_16M			(         BIT(1) | BIT(0))
-#define   SPI_SPEED_100M		(BIT(2)                  )
-#define   SPI_SPEED_800K		(BIT(2) |          BIT(0))
-#define   SPI_NORM_SPEED_NEW_SH		12
-#define   SPI_FAST_SPEED_NEW_SH		8
-#define   SPI_ALT_SPEED_NEW_SH		4
-#define   SPI_TPM_SPEED_NEW_SH		0
+enum spi100_speed {
+	SPI_SPEED_66M = 0,
+	SPI_SPEED_33M = 1,
+	SPI_SPEED_22M = 2,
+	SPI_SPEED_16M = 3,
+	SPI_SPEED_100M = 4,
+	SPI_SPEED_800K = 5,
+};
+
+#define   SPI_SPEED_MASK		0xf
+#define   SPI_SPEED_MODE(x, shift)	(((x) & SPI_SPEED_MASK) << (shift))
+#define   SPI_NORM_SPEED(x)		SPI_SPEED_MODE(x, 12)
+#define   SPI_FAST_SPEED(x)		SPI_SPEED_MODE(x, 8)
+#define   SPI_ALT_SPEED(x)		SPI_SPEED_MODE(x, 4)
+#define   SPI_TPM_SPEED(x)		SPI_SPEED_MODE(x, 0)
+
+#define   SPI_SPEED_CFG(n, f, a, t)	(SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \
+					 SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t))
 
 #define SPI100_HOST_PREF_CONFIG		0x2c
 #define   SPI_RD4DW_EN_HOST		BIT(15)
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 6bedab0629..caf7171c94 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -214,11 +214,8 @@ static uintptr_t sb_init_spi_base(void)
 void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
 {
 	uintptr_t base = sb_init_spi_base();
-	write16((void *)(base + SPI100_SPEED_CONFIG),
-				(norm << SPI_NORM_SPEED_NEW_SH) |
-				(fast << SPI_FAST_SPEED_NEW_SH) |
-				(alt << SPI_ALT_SPEED_NEW_SH) |
-				(tpm << SPI_TPM_SPEED_NEW_SH));
+
+	write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm));
 	write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100);
 }
 
@@ -233,9 +230,9 @@ void sb_disable_4dw_burst(void)
 void sb_read_mode(u32 mode)
 {
 	uintptr_t base = sb_init_spi_base();
-	write32((void *)(base + SPI_CNTRL0),
-			(read32((void *)(base + SPI_CNTRL0))
-					& ~SPI_READ_MODE_MASK) | mode);
+	uint32_t val = (read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK);
+
+	write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode));
 }
 
 static void fch_smbus_init(void)