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authorRaul E Rangel <rrangel@chromium.org>2021-04-02 10:55:27 -0600
committerRaul Rangel <rrangel@chromium.org>2021-04-05 16:38:23 +0000
commit61ac1bc53022f3baa0e5a753bd75d639cb95718a (patch)
treeddc0136343218a0c50635b0ec7465b2a9206ba7f /src/soc/amd/picasso
parentc988d0516cd91c9d2d7c8ace8c958fc2226996cc (diff)
soc/amd: Make espi_configure_decodes private
This is only ever called after espi_setup. 55861 - AMD System Peripheral Bus Overview also says that io ranges should be configured before enabling the BUS_MASTER bit. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/picasso')
-rw-r--r--src/soc/amd/picasso/early_fch.c4
-rw-r--r--src/soc/amd/picasso/psp_verstage/fch.c4
2 files changed, 2 insertions, 6 deletions
diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c
index 63e192fa7f..5f47638e7e 100644
--- a/src/soc/amd/picasso/early_fch.c
+++ b/src/soc/amd/picasso/early_fch.c
@@ -77,8 +77,6 @@ void fch_early_init(void)
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
- if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
+ if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
espi_setup();
- espi_configure_decodes();
- }
}
diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c
index e6c70f62ee..a032bde9b2 100644
--- a/src/soc/amd/picasso/psp_verstage/fch.c
+++ b/src/soc/amd/picasso/psp_verstage/fch.c
@@ -153,8 +153,6 @@ uint32_t verstage_soc_early_init(void)
void verstage_soc_init(void)
{
- if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
+ if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
espi_setup();
- espi_configure_decodes();
- }
}