diff options
author | Zheng Bao <zheng.bao@amd.com> | 2020-06-09 09:47:06 +0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-10 21:20:19 +0000 |
commit | 6ba591b4472c7b8442de860c1a401340be5e5c25 (patch) | |
tree | bdd6bb711bcafb251c43d21221e0b3677d799cab /src/soc/amd/picasso/update_microcode.c | |
parent | a5b7ddf94047aed0444b0fd44c3498a639577d58 (diff) |
amd/picasso: Load x86 microcode from CBFS modules
Combine the Ucode binaries for 3 revisions of CPU into one
CBFS module.
This should be moved to the AMD common code later.
BUG=b:153580119
TEST=mandolin
Change-Id: Ib08a65b93c045afc97952a809670c85831c0faf7
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/picasso/update_microcode.c')
-rw-r--r-- | src/soc/amd/picasso/update_microcode.c | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/update_microcode.c b/src/soc/amd/picasso/update_microcode.c new file mode 100644 index 0000000000..8f3d3e22b8 --- /dev/null +++ b/src/soc/amd/picasso/update_microcode.c @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <cpu/amd/microcode.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> +#include <cbfs.h> + +#define MPB_MAX_SIZE 3200 +#define MPB_DATA_OFFSET 32 + +struct microcode { + uint32_t date_code; + uint32_t patch_id; + + uint16_t mc_patch_data_id; + uint8_t reserved1[6]; + + uint32_t chipset1_dev_id; + uint32_t chipset2_dev_id; + + uint16_t processor_rev_id; + + uint8_t chipset1_rev_id; + uint8_t chipset2_rev_id; + + uint8_t reserved2[4]; + + uint8_t m_patch_data[MPB_MAX_SIZE-MPB_DATA_OFFSET]; +} __packed; + +static void apply_microcode_patch(const struct microcode *m) +{ + uint32_t new_patch_id; + msr_t msr; + + msr.hi = (uint64_t)(uintptr_t)m >> 32; + msr.lo = (uintptr_t)m & 0xffffffff; + + wrmsr(MSR_PATCH_LOADER, msr); + + printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", + m->patch_id); + + msr = rdmsr(MSR_PATCH_LEVEL); + new_patch_id = msr.lo; + + if (new_patch_id == m->patch_id) + printk(BIOS_INFO, "microcode: being updated to patch id = 0x%08x succeeded\n", + new_patch_id); + else + printk(BIOS_ERR, "microcode: being updated to patch id = 0x%08x failed\n", + new_patch_id); +} + +static uint16_t get_equivalent_processor_rev_id(void) +{ + uint32_t cpuid_family = cpuid_eax(1); + + return (uint16_t)((cpuid_family & 0xff0000) >> 8 | (cpuid_family & 0xff)); +} + +static void amd_update_microcode(const void *ucode, size_t ucode_len, + uint16_t equivalent_processor_rev_id) +{ + const struct microcode *m; + + for (m = (struct microcode *)ucode; + m < (struct microcode *)ucode + ucode_len/MPB_MAX_SIZE; m++) { + if (m->processor_rev_id == equivalent_processor_rev_id) + apply_microcode_patch(m); + } +} + +void amd_update_microcode_from_cbfs(void) +{ + const void *ucode; + size_t ucode_len; + uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id(); + + ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", + CBFS_TYPE_MICROCODE, &ucode_len); + if (!ucode) { + printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n"); + return; + } + + amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); +} |