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authorFelix Held <felix-coreboot@felixheld.de>2021-05-28 19:10:13 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-06-02 15:27:26 +0000
commitaea59401d053690ce06a5f89be272865e7905682 (patch)
tree29cf83b6d5aa80c5ec247a084a2ee758c72428a7 /src/soc/amd/picasso/reset.c
parent71971c9d7e3102f4568d24107dec9ac44277d073 (diff)
soc/amd/picasso: remove warm reset flag code
Since the MCA(X) registers have defined values on the cold boot path, the is_warm_reset check can be dropped. Also the warm reset bit in the NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if something was written to the register or the machine went through a warm reset cycle, the NCP_WARM_BOOT bit never got set. [1] checked with PPR for AMD Family 17h Models 11h,18h B1 (RV,PCO) #55570 Rev 3.15 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/reset.c')
-rw-r--r--src/soc/amd/picasso/reset.c14
1 files changed, 0 insertions, 14 deletions
diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c
index 84226ea6df..8181d90ee7 100644
--- a/src/soc/amd/picasso/reset.c
+++ b/src/soc/amd/picasso/reset.c
@@ -7,18 +7,6 @@
#include <amdblocks/acpimmio.h>
#include <amdblocks/reset.h>
-void set_warm_reset_flag(void)
-{
- uint8_t ncp = inb(NCP_ERR);
-
- outb(NCP_ERR, ncp | NCP_WARM_BOOT);
-}
-
-int is_warm_reset(void)
-{
- return !!(inb(NCP_ERR) & NCP_WARM_BOOT);
-}
-
void do_cold_reset(void)
{
/* De-assert and then assert all PwrGood signals on CF9 reset. */
@@ -29,8 +17,6 @@ void do_cold_reset(void)
void do_warm_reset(void)
{
- set_warm_reset_flag();
-
/* Assert reset signals only. */
outb(RST_CPU | SYS_RST, RST_CNT);
}