diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-11-30 18:18:35 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-02 21:27:03 +0000 |
| commit | 6443ad4a53ab65a2a9c1d29f422644e450c04cd7 (patch) | |
| tree | 4843082fa04ab74fd08b53aa01eb65165e8edb4f /src/soc/amd/picasso/include | |
| parent | 5b3831c75abe5fc50739984eaa70fbada2575bb7 (diff) | |
soc/amd: factor out common AOAC device enable and status query functions
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits
to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is
the default value after reset for those bits on both platforms.
Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 8a2ae49b3f..809eb97486 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -247,9 +247,6 @@ typedef struct aoac_devs { } __packed aoac_devs_t; void enable_aoac_devices(void); -bool is_aoac_device_enabled(unsigned int dev); -void power_on_aoac_device(unsigned int dev); -void power_off_aoac_device(unsigned int dev); void wait_for_aoac_enabled(unsigned int dev); void sb_clk_output_48Mhz(void); void sb_enable(struct device *dev); |