diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-07-16 15:18:00 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-09 20:24:59 +0000 |
| commit | 34c30565b0ef3b1ff79943768ecc2f4012bf6b86 (patch) | |
| tree | dcf063fd97bba7206fed1656eb50171db01287ee /src/soc/amd/picasso/include | |
| parent | 0bd0806d2f8158cf43f52fc3106fc759bd6c4a94 (diff) | |
soc/amd/picasso: Update CPU support
Change the Stoney Ridge ID to Picasso. Rename family 15h. Get the
number of cores/threads from CPUID as all D18 registers are new.
Change-Id: I44c45db637897f6caf320032c9f79a3a1ab4d6c9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/cpu.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/northbridge.h | 4 |
2 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 7bc1810dba..e57d2d3187 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -22,6 +22,7 @@ #define SOC_EARLY_VMTRR_TEMPRAM 2 void picasso_init_cpus(struct device *dev); +int get_cpu_count(void); void check_mca(void); #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 667a49eb0c..e423ab1aa7 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -73,10 +73,6 @@ #define D18F1_VGAEN 0xf4 # define VGA_ADDR_ENABLE (1 << 0) -/* D18F5 */ -#define NB_CAPABILITIES2 0x84 -#define CMP_CAP_MASK 0xff - void amd_initcpuio(void); void domain_enable_resources(struct device *dev); |