diff options
| author | Rob Barnes <robbarnes@google.com> | 2020-01-30 10:54:28 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-09-17 12:35:56 +0000 |
| commit | 28cb14bf133f63f9451610348f9a84370c4b3c59 (patch) | |
| tree | 69e74d71272944100a0e5e3ad1ac87d7f053210e /src/soc/amd/picasso/include | |
| parent | 60795784b7ecca79572c86715b6dfd6d41ae2055 (diff) | |
soc/amd/picasso: Clean up legacy UART config
Clean up configuration of the legacy UART and add Kconfig options for
the mapping between UART and legacy I/O decode.
BUG=b:143283592
BUG=b:153675918
TEST=Linux detects an additional legacy serial port for each active MMIO
one if PICASSO_UART_LEGACY is selected.
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2
Reviewed-on: https://chromium-review.googlesource.com/2037891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 547f602db7..222858ab51 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -221,10 +221,14 @@ #define FCH_AOAC_STAT0 BIT(6) #define FCH_AOAC_STAT1 BIT(7) -#define FCH_UART_LEGACY_DECODE 0xfedc0020 -#define FCH_LEGACY_3F8_SH 3 -#define FCH_LEGACY_2F8_SH 1 -#define FCH_LEGACY_3E8_SH 2 +#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ +#define FCH_LEGACY_UART_MAP_SHIFT 8 +#define FCH_LEGACY_UART_MAP_SIZE 2 +#define FCH_LEGACY_UART_MAP_MASK 0x3 +#define FCH_LEGACY_UART_RANGE_2E8 0 +#define FCH_LEGACY_UART_RANGE_2F8 1 +#define FCH_LEGACY_UART_RANGE_3E8 2 +#define FCH_LEGACY_UART_RANGE_3F8 3 #define PM1_LIMIT 16 #define GPE0_LIMIT 28 @@ -279,6 +283,7 @@ void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); void fch_pre_init(void); void fch_early_init(void); +void set_uart_legacy_config(unsigned int uart_idx, unsigned int range_idx); /* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); |