diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-18 01:34:06 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-19 15:37:15 +0000 |
| commit | 0e099eaf83c732599b47f2d5301871d6076857a8 (patch) | |
| tree | 0205ad2e102539f0b24da27664cf5484c694315a /src/soc/amd/picasso/include | |
| parent | 2f8a7046bb120d96022ada1e74545f859f97521f (diff) | |
soc/amd/picasso: move gpp_clk_req_setting definition to chip.h
Since this enum is only used for the devicetree settings and not for the
hardware itself, move it from the southbridge header to the chip one.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0907fc5cba9315fec5fabff67d279c6d95d1c9f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54684
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/picasso/include')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index e2a069baff..11660aa8bb 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -143,13 +143,6 @@ /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT BIT(7) /* Write-once */ -/* this is for the devicetree setting and not the values written to the register */ -enum gpp_clk_req_setting { - GPP_CLK_ON, /* GPP clock always on; default */ - GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ - GPP_CLK_OFF, /* GPP clk off */ -}; - typedef struct aoac_devs { unsigned int :7; unsigned int ic2e:1; /* 7: I2C2 */ |