diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-20 20:47:22 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-06 12:12:10 +0000 |
| commit | c5d71dc7ff9bc253a9151d1da9f55b0c59406820 (patch) | |
| tree | 30ae10ccaaeacda543f2de7a5f8e842024df5f9e /src/soc/amd/picasso/acpi | |
| parent | f56b645f1fe0f70f4b8225ec5f3ee31b31db3d13 (diff) | |
soc/amd/picasso: remove LIDS field from global NVS
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Picasso SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/acpi')
| -rw-r--r-- | src/soc/amd/picasso/acpi/globalnvs.asl | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index f616361ec6..2d24b888fd 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -9,11 +9,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - LIDS, 8, // 0x00 - LID State - CBMC, 32, // 0x01 - 0x04 - coreboot Memory Console - PM1I, 64, // 0x05 - 0x0c - System Wake Source - PM1 Index - GPEI, 64, // 0x0d - 0x14 - GPE Wake Source - TMPS, 8, // 0x15 - Temperature Sensor ID - TCRT, 8, // 0x16 - Critical Threshold - TPSV, 8, // 0x17 - Passive Threshold + CBMC, 32, // 0x00 - 0x03 - coreboot Memory Console + PM1I, 64, // 0x04 - 0x0b - System Wake Source - PM1 Index + GPEI, 64, // 0x0c - 0x13 - GPE Wake Source + TMPS, 8, // 0x14 - Temperature Sensor ID + TCRT, 8, // 0x15 - Critical Threshold + TPSV, 8, // 0x16 - Passive Threshold } |