diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2020-03-09 13:50:31 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-05-20 00:16:53 +0000 |
| commit | 28d4275622dd66132b2849c09b33684dd6553ff1 (patch) | |
| tree | 6d7ca99a3247098783fc8f9ae474af2803828b3f /src/soc/amd/picasso/acpi/pcie.asl | |
| parent | 839f668d89e8cfb6fcd3aeaa21148d7644cb040e (diff) | |
soc/amd/picasso/acpi: Improve PCI Interrupt Link Devices
The PCI interrupt devices were only partially implemented.
* Lacked support for _DIS to disable the bus. Something the kernel does
while booting.
* Lacked support for APIC vs PIC. This means the devices can only be
used when using the PIC. By looking at the PMOD variable we can handle
both PIC and APIC. This means we can stop hard coding the PCI interrupt
numbers in the ACPI tables.
* I removed INT[E-H] since they are not used.
BUG=b:139429446, b:147042464
BRANCH=none
TEST=Boot with both the APIC and PIC and saw that the link devices work
as expected:
PIC MODE:
[ 1.959345] ACPI: PCI Interrupt Link [IRQA] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15)
[ 2.007344] ACPI: PCI Interrupt Link [IRQB] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15)
[ 2.056344] ACPI: PCI Interrupt Link [IRQC] (IRQs 1 3 4 5 6 7 8 9 10 11 12 *14 15)
[ 2.104344] ACPI: PCI Interrupt Link [IRQD] (IRQs 1 3 4 5 6 7 8 9 10 11 12 14 *15)
[ 13.752676] PCI Interrupt Link [IRQA] enabled at IRQ 6
[ 13.816755] PCI Interrupt Link [IRQD] enabled at IRQ 15
[ 27.788798] PCI Interrupt Link [IRQB] enabled at IRQ 6
[ 27.852873] PCI Interrupt Link [IRQC] enabled at IRQ 14
APIC MODE:
[ 19.311764] ACPI: PCI Interrupt Link [IRQA] (IRQs *16 17 18 19 20 21 22 23)
[ 19.374765] ACPI: PCI Interrupt Link [IRQB] (IRQs 16 *17 18 19 20 21 22 23)
[ 19.438770] ACPI: PCI Interrupt Link [IRQC] (IRQs 16 17 *18 19 20 21 22 23)
[ 19.501764] ACPI: PCI Interrupt Link [IRQD] (IRQs 16 17 18 *19 20 21 22 23)
[ 34.719072] PCI Interrupt Link [IRQA] enabled at IRQ 23
[ 34.798994] PCI Interrupt Link [IRQD] enabled at IRQ 22
[ 66.469510] PCI Interrupt Link [IRQB] enabled at IRQ 21
[ 66.542395] PCI Interrupt Link [IRQC] enabled at IRQ 20
Change-Id: I1bb84813b65c89b4b5479602be3e9a9fedb7333d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095683
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/picasso/acpi/pcie.asl')
| -rw-r--r-- | src/soc/amd/picasso/acpi/pcie.asl | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index ecb54b9e16..2bbfec56e4 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -7,14 +7,25 @@ PRQD, 0x00000008, /* Offset: 1h */ } IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ + PIRA, 0x00000008, /* Index 0: INTA */ + PIRB, 0x00000008, /* Index 1: INTB */ + PIRC, 0x00000008, /* Index 2: INTC */ + PIRD, 0x00000008, /* Index 3: INTD */ + PIRE, 0x00000008, /* Index 4: INTE */ + PIRF, 0x00000008, /* Index 5: INTF */ + PIRG, 0x00000008, /* Index 6: INTG */ + PIRH, 0x00000008, /* Index 7: INTH */ + + /* IO-APIC IRQs */ + Offset (0x80), + IORA, 0x00000008, /* Index 0x80: INTA */ + IORB, 0x00000008, /* Index 0x81: INTB */ + IORC, 0x00000008, /* Index 0x82: INTC */ + IORD, 0x00000008, /* Index 0x83: INTD */ + IORE, 0x00000008, /* Index 0x84: INTE */ + IORF, 0x00000008, /* Index 0x85: INTF */ + IORG, 0x00000008, /* Index 0x86: INTG */ + IORH, 0x00000008, /* Index 0x87: INTH */ } /* PCI Error control register */ |