diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-12 14:37:43 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-14 18:05:17 +0000 |
| commit | 394c6b092251f0da8f0bd159e0eb08a41a6e4afc (patch) | |
| tree | e9d347574e889fc911ebe512d2bfc012239a5d73 /src/soc/amd/picasso/Kconfig | |
| parent | 844775059d8cb456dec988e6378f3a73ea730001 (diff) | |
soc/amd: Move update_microcode.c to common/block/cpu
We also want to support uCode loading on cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/picasso/Kconfig')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index d037d48990..16a12972b4 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART + select SOC_AMD_COMMON_BLOCK_UCODE select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -58,7 +59,9 @@ config CPU_SPECIFIC_OPTIONS select FSP_COMPRESS_FSP_S_LZMA select UDK_2017_BINDING select HAVE_CF9_RESET - select SUPPORT_CPU_UCODE_IN_CBFS + +config SOC_AMD_COMMON_BLOCK_UCODE_SIZE + default 3200 config FSP_M_FILE string "FSP-M (memory init) binary path and filename" |