diff options
| author | Martin Roth <gaumless@gmail.com> | 2023-04-19 13:40:06 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-21 15:33:09 +0000 |
| commit | cc827d9aab1f0ef25a77ebc64755cf4454857f4b (patch) | |
| tree | 1619bccb96df348853d14ba3ef771966d11411a7 /src/soc/amd/phoenix | |
| parent | c9ce5f6ec8f60cfd56eca127680032b3c6ed38de (diff) | |
soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off
When one of the General-Purpose PCIe bridges is not used, it doesn't
show up on the PCI bus at all, so coreboot notes it as an issue in the
devicetree. This happens even if the device is marked as off.
To solve this, we're marking the GPP bridge devices in devicetree as
hidden, so they'll only show up in devicetree if they're actually used
on a mainboard.
BUG=b:277997811
TEST=Build
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74527
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/phoenix')
| -rw-r--r-- | src/soc/amd/phoenix/chipset.cb | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 055e125f04..97b7ec14fd 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -11,19 +11,19 @@ chip soc/amd/phoenix device pci 01.0 on end # Dummy Host Bridge, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers - device pci 01.1 alias gpp_bridge_1_1 off ops amd_external_pcie_gpp_ops end - device pci 01.2 alias gpp_bridge_1_2 off ops amd_external_pcie_gpp_ops end - device pci 01.3 alias gpp_bridge_1_3 off ops amd_external_pcie_gpp_ops end - device pci 01.4 alias gpp_bridge_1_4 off ops amd_external_pcie_gpp_ops end + device pci 01.1 alias gpp_bridge_1_1 hidden ops amd_external_pcie_gpp_ops end + device pci 01.2 alias gpp_bridge_1_2 hidden ops amd_external_pcie_gpp_ops end + device pci 01.3 alias gpp_bridge_1_3 hidden ops amd_external_pcie_gpp_ops end + device pci 01.4 alias gpp_bridge_1_4 hidden ops amd_external_pcie_gpp_ops end device pci 02.0 on end # Dummy Host Bridge, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers - device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_2_1 hidden ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_2_2 hidden ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2_3 hidden ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_2_4 hidden ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_2_5 hidden ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_2_6 hidden ops amd_external_pcie_gpp_ops end device pci 03.0 on end # Dummy Host Bridge, do not disable device pci 03.1 alias usb4_pcie_bridge_0 off end |