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authorFelix Held <felix-coreboot@felixheld.de>2024-02-01 20:24:34 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-02-02 20:37:37 +0000
commit5dc83818b8d14950bf10451f75901b52108b0697 (patch)
treeb8807b40cd98bb490fea58d39413506cef625176 /src/soc/amd/phoenix/acpi.c
parent2911823289d6469970f46514193705c863c42113 (diff)
soc/amd/phoenix: add openSIL calls
Add the calls to the openSIL stubs to do the silicon initialization, to get the APCI IO ports, and to get the memory map. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6f37bf211e130cb44927f8a0e7f9134d246dfc1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80296 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/phoenix/acpi.c')
-rw-r--r--src/soc/amd/phoenix/acpi.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index a6482ee67d..606a45ff62 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <soc/iomap.h>
#include <types.h>
+#include <vendorcode/amd/opensil/genoa_poc/opensil.h>
#include "chip.h"
/*
@@ -29,12 +30,17 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{
const struct soc_amd_phoenix_config *cfg = config_of_soc();
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
+ if (CONFIG(PLATFORM_USES_FSP2_0)) {
+ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
- fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
- fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
- fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
- fadt->gpe0_blk = ACPI_GPE0_BLK;
+ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+ fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+ fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+ fadt->gpe0_blk = ACPI_GPE0_BLK;
+ } else {
+ /* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */
+ opensil_fill_fadt_io_ports(fadt);
+ }
fadt->pm1_evt_len = 4; /* 32 bits */
fadt->pm1_cnt_len = 2; /* 16 bits */