soc/amd/*/Kconfig: rework SPL options

Move all security patch level (SPL) related Kconfig options to the
common AMD PSP Kconfig file. Commit 4ab1db82bb30 ("soc/amd: rework SPL
file override and SPL fusing handling") already reworked the SPL
handling, but missed that another Kconfig option
SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL controlled if the PSP mailbox command
to update the SPL fuses was sent by the code that got added to the build
when PERFORM_SPL_FUSING was selected.

To make things less unexpected, rename PERFORM_SPL_FUSING to
SOC_AMD_COMMON_BLOCK_PSP_SPL since it actually controls if the SPL
support code is added to the build and also rename
SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL to PERFORM_SPL_FUSING. This changes
what PERFORM_SPL_FUSING will do from including the code that could do
the fusing if another option is set to being the option that controls if
the fusing mailbox command will be set. All SoCs that support SPL now
select SOC_AMD_COMMON_BLOCK_PSP_SPL in their Kconfig, which won't burn
any SPL fuses.

The logic in the Skyrim mainboard Kconfig file is reworked to select
PERFORM_SPL_FUSING for all boards on which the SPL fuses should be
updated; on Guybrush PERFORM_SPL_FUSING default is changed to y for all
variants. The option to include the code that checks the SPL fusing
conditions and allows sending the command to update the SPL fuses if the
corresponding Kconfig is set doesn't need to be added on the mainboard
level, since it's already selected at the SoC level.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12fd8775db66f16fe632674cd67c6af483e8d4e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

1 files changed, 1 insertions, 33 deletions

diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index c9aa32c770..9137bc5ce7 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -64,6 +64,7 @@ config SOC_AMD_PHOENIX
 	select SOC_AMD_COMMON_BLOCK_PM
 	select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN2		# TODO: Check if this is still correct
+	select SOC_AMD_COMMON_BLOCK_PSP_SPL
 	select SOC_AMD_COMMON_BLOCK_RESET
 	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_SMI
@@ -362,39 +363,6 @@ config PSP_WHITELIST_FILE
 	depends on HAVE_PSP_WHITELIST_FILE
 	default "site-local/3rdparty/amd_blobs/phoenix/PSP/wtl-phx.sbin"
 
-config PERFORM_SPL_FUSING
-	bool "Send SPL fuse command to PSP"
-	default n
-	help
-	  Send the Security Patch Level (SPL) fusing command to the PSP in
-	  order to update the minimum SPL version to be written to the SoC's
-	  fuse bits. This will prevent using any embedded firmware components
-	  with lower SPL version.
-
-	  If unsure, answer 'n'
-
-config SPL_TABLE_FILE
-	string "SPL table file override"
-	help
-	  Provide a mainboard-specific Security Patch Level (SPL) table file
-	  override. The SPL file is required to support PSP FW anti-rollback
-	  and needs to be created by AMD. The default SPL file specified in the
-	  SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule
-	  and applies to all boards that use the SoC without verstage on PSP.
-	  In the verstage on PSP case, a different SPL file is specific as an
-	  override via this Kconfig option.
-
-config HAVE_SPL_RW_AB_FILE
-	bool "Have a separate mainboard-specific SPL file in RW A/B partitions"
-	default n
-	depends on VBOOT_SLOTS_RW_AB
-	help
-	  Have separate mainboard-specific Security Patch Level (SPL) table
-	  file for the RW A/B FMAP partitions.
-
-config SPL_RW_AB_TABLE_FILE
-	string "Separate SPL table file override for RW A/B partitions"
-
 config PSP_SOFTFUSE_BITS
 	string "PSP Soft Fuse bits to enable"
 	default "36 28 6"