diff options
| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-12-07 08:39:55 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-13 17:43:11 +0000 |
| commit | a6514e2b1f79c6112768f3b7bc47310c06c2c3a2 (patch) | |
| tree | 6d8881b33bf98ce4775696b4d93cc11920a931b1 /src/soc/amd/morgana/include | |
| parent | 8ff89378439f18517d14375d37c352dd6d75c95b (diff) | |
soc/amd/morgana: Enable GPP clk req disabling
Enable GPP clk req disabling on morgana after reviewing against morgana
ppr #57396, rev 1.52
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/morgana/include')
| -rw-r--r-- | src/soc/amd/morgana/include/soc/southbridge.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/soc/amd/morgana/include/soc/southbridge.h b/src/soc/amd/morgana/include/soc/southbridge.h index 216bf42677..b64d38a8f7 100644 --- a/src/soc/amd/morgana/include/soc/southbridge.h +++ b/src/soc/amd/morgana/include/soc/southbridge.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Morgana */ - #ifndef AMD_MORGANA_SOUTHBRIDGE_H #define AMD_MORGANA_SOUTHBRIDGE_H @@ -13,7 +11,7 @@ #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) #define PWR_RESET_CFG 0x10 -#define TOGGLE_ALL_PWR_GOOD (1 << 1) +#define TOGGLE_ALL_PWR_GOOD BIT(1) #define PM_SERIRQ_CONF 0x54 #define PM_SERIRQ_NUM_BITS_17 0x0000 #define PM_SERIRQ_NUM_BITS_18 0x0004 @@ -61,7 +59,6 @@ #define PM_ACPI_SW_S5PWRMUX BIT(16) #define PM_ACPI_EN_SHUTDOWN_MSG BIT(17) #define PM_ACPI_EN_SYNC_FLOOD BIT(18) -#define PM_ACPI_FORCE_SPIUSEPIN_0 BIT(19) #define PM_ACPI_EN_DF_INTRWAKE BIT(20) #define PM_ACPI_MASK_USB_S5_RST BIT(21) #define PM_ACPI_USE_RSMU_RESET BIT(22) @@ -96,7 +93,7 @@ #define GPP_CLK5_REQ_SHIFT 10 #define GPP_CLK6_REQ_SHIFT 12 #define GPP_CLK_OUTPUT_COUNT 7 -#define GPP_CLK_OUTPUT_AVAILABLE 4 +#define GPP_CLK_OUTPUT_AVAILABLE 7 #define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) |