diff options
| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-12-07 08:39:55 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-13 17:43:11 +0000 |
| commit | a6514e2b1f79c6112768f3b7bc47310c06c2c3a2 (patch) | |
| tree | 6d8881b33bf98ce4775696b4d93cc11920a931b1 /src/soc/amd/morgana/fch.c | |
| parent | 8ff89378439f18517d14375d37c352dd6d75c95b (diff) | |
soc/amd/morgana: Enable GPP clk req disabling
Enable GPP clk req disabling on morgana after reviewing against morgana
ppr #57396, rev 1.52
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/morgana/fch.c')
| -rw-r--r-- | src/soc/amd/morgana/fch.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/amd/morgana/fch.c b/src/soc/amd/morgana/fch.c index 08fbe9816e..b740f47942 100644 --- a/src/soc/amd/morgana/fch.c +++ b/src/soc/amd/morgana/fch.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Morgana */ - #include <amdblocks/acpi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> +#include <amdblocks/pci_clk_req.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -125,7 +124,7 @@ static void fch_init_acpi_ports(void) /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { - const struct soc_amd_morgana_config *cfg = config_of_soc(); + struct soc_amd_morgana_config *cfg = config_of_soc(); /* look-up table to be able to iterate over the PCIe clock output settings */ const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { @@ -140,6 +139,8 @@ static void gpp_clk_setup(void) uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); + pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], + ARRAY_SIZE(cfg->gpp_clk_config)); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); /* |