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authorFelix Held <felix-coreboot@felixheld.de>2023-01-19 18:15:17 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-01-20 17:40:29 +0000
commitb2394e853bf7652fa70295d34892a8385b9a5153 (patch)
tree462a4a2667a94618cc37985ace36d18a0c9268d2 /src/soc/amd/mendocino
parent703778cb839b29bb2d80be90155667121c3f90b0 (diff)
soc/amd/cezanne: clean up global NVS
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4034e959d167fb1e08ee5b15e21fb93bc89db8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72093 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/mendocino')
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