diff options
| author | Varshit Pandya <pandyavarshit@gmail.com> | 2024-02-08 21:32:57 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-10 16:53:22 +0000 |
| commit | 0452d0939e7d7ddbf24d78ad5e69408b5ad52f47 (patch) | |
| tree | ef428728d58e7e955bc26cc909380a45c5a37194 /src/soc/amd/mendocino/include | |
| parent | 9f297080aa1ec6b45551f7a177a21394e627c3e2 (diff) | |
soc/amd: Factor out gpp_clk_setup function
gpp_clk_setup code in most AMD SoC is similar and it can moved to common
code. The only thing which is SoC dependent in this function is the SoC
config, hence keep it in SoC code and move everything else in new
gpp_clk_setup_common function which is in soc/amd/common. Picasso and
Glinda don't have pcie_gpp_dxio_update_clk_req_config fixup function so
they are addressed in later patches.
Change-Id: I7d7da4bfe079f07e31212247dbf3acd14daa6447
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80285
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/mendocino/include')
| -rw-r--r-- | src/soc/amd/mendocino/include/soc/southbridge.h | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/src/soc/amd/mendocino/include/soc/southbridge.h b/src/soc/amd/mendocino/include/soc/southbridge.h index 2e88c77329..9b276d2636 100644 --- a/src/soc/amd/mendocino/include/soc/southbridge.h +++ b/src/soc/amd/mendocino/include/soc/southbridge.h @@ -85,20 +85,7 @@ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ /* FCH MISC Registers 0xfed80e00 */ -#define GPP_CLK_CNTRL 0x00 -#define GPP_CLK0_REQ_SHIFT 0 -#define GPP_CLK1_REQ_SHIFT 2 -#define GPP_CLK4_REQ_SHIFT 4 -#define GPP_CLK2_REQ_SHIFT 6 -#define GPP_CLK3_REQ_SHIFT 8 -#define GPP_CLK5_REQ_SHIFT 10 -#define GPP_CLK6_REQ_SHIFT 12 -#define GPP_CLK_OUTPUT_COUNT 7 #define GPP_CLK_OUTPUT_AVAILABLE 4 -#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) -#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) -#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) -#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift)) #define MISC_CLKGATEDCNTL 0x2c #define ALINKCLK_GATEOFFEN BIT(16) |